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-- Company: 
-- Engineer: 
-- 
-- Create Date:    13:59:57 04/10/2010 
-- Design Name: 
-- Module Name:    multiplier_sim - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity multiplier is
    Port ( CLOCK : in  STD_LOGIC;
           M_A : in  STD_LOGIC_VECTOR (15 downto 0);
           M_B : in  STD_LOGIC_VECTOR (15 downto 0);
           M_P : out  STD_LOGIC_VECTOR (31 downto 0));
end multiplier;

architecture Behavioral of multiplier is
begin

PROCESS (CLOCK)
	variable pipe0 : SIGNED(31 downto 0);
	variable pipe1 : SIGNED(31 downto 0);
	variable pipe2 : SIGNED(31 downto 0);
	variable pipe3 : SIGNED(31 downto 0);
BEGIN
	IF rising_edge(CLOCK) THEN
		pipe3 := pipe2;
		pipe2 := pipe1;
		pipe1 := pipe0;
		pipe0 := SIGNED(M_A) * SIGNED(M_B);
		M_P <= STD_LOGIC_VECTOR(pipe3);
	END IF;
END PROCESS;

end Behavioral;

